D12320VF25V Datasheet, PDF (432/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 8-Bit Timers
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and
control compare match output.
TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.
Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and
TCORB match.
Bit 7
CMFB
0
1
Description
[Clearing conditions]
(Initial value)
• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
• When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORB
Bit 6—Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and
TCORA match.
Bit 6
CMFA
0
1
Description
[Clearing conditions]
(Initial value)
• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
• When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORA
Bit 5—Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed
from H'FF to H'00).
Bit 5
OVF
0
1
Description
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 to OVF
[Setting condition]
Set when TCNT overflows from H'FF to H'00
(Initial value)
Rev.7.00 Feb. 14, 2007 page 398 of 1108
REJ09B0089-0700