D12320VF25V Datasheet, PDF (1029/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

DTVECR—DTC Vector Register
Appendix B Internal I/O Registers
H'FF37
DTC
Bit
:7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value : 0
0
0
0
0
0
0
0
Read/Write : R/W R/(W)* R/(W)* R/(W)* R/(W)* _R/(W)* _R/(W)* R/(W)*
Sets vector number for DTC software activation
DTC Software Activation Enable
0 DTC software activation is disabled
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of transfers have
not ended
• When 0 is written to the SWDTE bit after a software activated data
transfer end interrupt (SWDTEND) has been requested of the CPU
1 DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation
Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
Rev.7.00 Feb. 14, 2007 page 995 of 1108
REJ09B0089-0700