D12320VF25V Datasheet, PDF (633/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU bit in FLMCR1
Wait (y) μs
*6
Set P bit in FLMCR1
Wait (z1) μs or (z2) μs or (z3) μs *5 *6
Clear P bit in FLMCR1
Wait (α) μs
*6
Clear PSU bit in FLMCR1
Wait (β) μs
*6
Disable WDT
End sub
Start of programming
Start
Set SWE bit in FLMCR1
Wait (x) μs
*6
Store 128-byte program data in program
data area and reprogram data area
*4
n=1
Perform programming in
the erased state.
Do not perform additional
programming
on previously programmed
addresses.
m=0
Write 128-byte data in RAM reprogram _*1
data area consecutively to flash memory
Sub-routine-call
Write pulse
(z1) μs or (z2) μs
See Note *7 for pulse width
*6
Set PV bit in FLMCR1
Wait (γ) μs
*6
Note: 7. Write Pulse Width
*6
Number of Writes (n)
1
2
3
4
5
6
7
8
9
10
11
12
1_...3
998
999
1000
Write Time (z) μs
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z...2
z2
z2
z2
Note: Use a (z3) μs write pulse for additional
programming.
Increment address
H'FF dummy write to verify address
Wait (ε) μs
*6
Read verify data
*2
Read data = verify
NG
data?
OK
NG
6≥n?
OK
Additional program data computation
m=1
Transfer additional program data to
additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram _*4
data area
n←n+1
RAM
Program data area
(128 bytes)
Reprogram data area
(128 bytes)
128-byte
data verification
NG
completed?
OK
Clear PV bit in FLMCR1
Wait (η) μs
*6
Additional program data
area (128 bytes)
NG
6≥n?
OK
Sequentially write 128-byte data in
additional program data area in RAM to *1
flash memory
Notes: 1. Data transfer is performed by byte transfer. The lower 8
bits of the first address written to must be H'00 or H'80. A
128-byte data transfer must be performed even if writing
fewer than 128 bytes; in this case, H'FF data must be
written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in
the 128-byte programming loop will be subjected to
additional programming if they fail the subsequent verify
operation.
Write Pulse
(z3) μs additional write pulse
*6
NG
m = 0?
OK
Clear SWE bit in FLMCR1
*6
n ≥ N?
NG
OK
Clear SWE bit in FLMCR1
4. A 128-byte area for storing program data, a 128-byte area
for storing reprogram data, and a 128-byte area for
Wait (θ) μs
*6
Wait (θ) μs
*6
storing additional program data should be provided in
RAM. The contents of the reprogram
End of programming
Programming failure
data and additional program data areas
are modified as programming proceeds.
5. A write pulse of (z1) or (z2) ms should
be applied according to the progress of
programming. See note 7 for the pulse
widths. When the additional program
data is programmed, a write pulse of
(z3) μs should be applied. Reprogram
data X' stands for reprogram data to
which a write pulse has been applied.
6. For the values of x, y, z1, z2, z3, α, β, γ,
ε, η, θ, and N, see section 20.3.6, Flash
Memory Characteristics.
Program Data Operation Chart
Original Data (D) Verify Data (V)
0
0
1
1
0
1
Reprogram Data (X)
1
0
1
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional Program Data Operation Chart
Reprogram Data (X') Verify Data (V) Additional Program Data (Y)
Comments
0
0
1
1
0
1
0
Additional programming executed
1
Additional programming not executed
Additional programming not executed
Additional programming not executed
Figure 17.15 Program/Program-Verify Flowchart
Rev.7.00 Feb. 14, 2007 page 599 of 1108
REJ09B0089-0700