D12320VF25V Datasheet, PDF (151/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.3 Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (43
sources).
5.3.1 External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to
restore the chip from software standby mode. (IRQ7 to IRQ3 can be designated for use as software
standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.)
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to
select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins
IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
IRQnSCA, IRQnSCB
IRQnE
IRQn input
Edge/level
detection circuit
IRQnF
S
Q
R
IRQn interrupt
request
Clear signal
Note: n = 7 to 0
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
Rev.7.00 Feb. 14, 2007 page 117 of 1108
REJ09B0089-0700