D12320VF25V Datasheet, PDF (1085/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TMDR0—Timer Mode Register 0
Appendix B Internal I/O Registers
H'FFD1
TPU0
Bit
:
7
⎯
Initial value :
1
Read/Write : _⎯
6
5
4
3
2
1
0
⎯
BFB BFA MD3 MD2 MD1 MD0
1
0
0
0
0
0
0
⎯
R/W R/W R/W R/W R/W R/W
Mode
0 0 0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
1 × × ×⎯
× : Don't care
Notes: 1. MD3 is a reserved bit. In a write, it
should always be written with 0.
2. Phase counting mode cannot be
set for channels 0 and 3. In this
case, 0 should always be written to
MD2.
TGRA Buffer Operation
0 TGRA operates normally
1 TGRA and TGRC used together
for buffer operation
TGRB Buffer Operation
0 TGRB operates normally
1 TGRB and TGRD used together
for buffer operation
Rev.7.00 Feb. 14, 2007 page 1051 of 1108
REJ09B0089-0700