D12320VF25V Datasheet, PDF (834/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 Clock Pulse Generator
18.4 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
18.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
18.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, φ/8, φ/16, or φ/32) to be supplied to the bus master, according to the settings of
the SCK2 to SCK0 bits in SCKCR.
Rev.7.00 Feb. 14, 2007 page 800 of 1108
REJ09B0089-0700