D12320VF25V Datasheet, PDF (1086/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TIOR0H—Timer I/O Control Register 0H
H'FFD2
TPU0
Bit
:
Initial value :
Read/Write :
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
TGR0A I/O Control
0 0 0 0 TGR0A Output disabled
is output
1
1
0
compare
register
Initial output is
0 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is
1 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0A _{Capture input}
is input
1 _capture
source is
TIOCA0 pin
1 × ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
TGR0B I/O Control
0 0 0 0 TGR0B Output disabled
is output
1 _compare Initial output is
1 0 ^{register 0 output}
1××
Capture input Input capture at TCNT1 count-up/
source is channel count-down
1/count clock
× : Don't care
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is
0 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0B Capture input
1
is input
capture
source is
TIOCB0 pin
1 × ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1××
Capture input Input capture at TCNT1 count-up/
source is channel count-down*
1/count clock
× : Don't care
Note: * When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and
input capture does not occur.
Rev.7.00 Feb. 14, 2007 page 1052 of 1108
REJ09B0089-0700