D12320VF25V Datasheet, PDF (1087/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TIOR0L—Timer I/O Control Register 0L
Appendix B Internal I/O Registers
H'FFD3
TPU0
Bit
:
:
Initial value :
Read/Write :
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
TGR0C I/O Control
0 0 0 0 TGR0C Output disabled
is output
1 _compare Initial output is
1 0 ^{register 0 output}
*1
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is
1 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0C Capture input
Input capture at rising edge
1
is input
capture
source is
TIOCC0 pin
Input capture at falling edge
1 × ^register
Input capture at both edges
*
1××
Capture input Input capture at TCNT1 count-up/
source is channel count-down
1/count clock
× : Don't care
TGR0D I/O Control
Note: * When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer
register, this setting is invalid and input capture/output compare does not
occur.
0 0 0 0 TGR0D Output disabled
is output
1 _compare Initial output is
1 0 ^{register 0 output}
*2
1
0 output at compare match
1 output at compare match
Toggle output at compare match
100
Output disabled
1
10
Initial output is
1 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0D Capture input
Input capture at rising edge
1
is input
capture
source is
TIOCD0 pin
Input capture at falling edge
1 × ^register
Input capture at both edges
*2
1××
Capture input
Input capture at TCNT1 count-up/
source is channel count-down*1
1/count clock
× : Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as
the TCNT1 count clock, this setting is invalid and input capture does not
occur.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer
register, this setting is invalid and input capture/output compare does not
occur.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Rev.7.00 Feb. 14, 2007 page 1053 of 1108
REJ09B0089-0700