D12320VF25V Datasheet, PDF (158/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.4 Interrupt Operation
5.4.1 Interrupt Control Modes and Interrupt Operation
Interrupt operations in the chip differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated
by the I bit in the CPU’s CCR, and bits I2 to I0 in EXR.
Table 5.5 Interrupt Control Modes
Interrupt
SYSCR _{Priority Setting}
Control Mode INTM1 INTM0 Registers
0
0
0
—
—
1
—
2
1
0
IPR
—
1
—
Interrupt
Mask Bits Description
I
Interrupt mask control is
performed by the I bit.
—
Setting prohibited
I2 to I0
8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set with
IPR.
—
Setting prohibited
Rev.7.00 Feb. 14, 2007 page 124 of 1108
REJ09B0089-0700