D12320VF25V Datasheet, PDF (208/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH
is set to 1, an idle cycle is inserted at the start of the write cycle.
Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
φ
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Long output
floating time
(a) Idle cycle not inserted
(ICIS0 = 0)
Data
collision
(b) Idle cycle inserted
(ICIS0 = 1 (initial value))
Figure 6.17 Example of Idle Cycle Operation (2)
Rev.7.00 Feb. 14, 2007 page 174 of 1108
REJ09B0089-0700