D12320VF25V Datasheet, PDF (464/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Watchdog Timer
11.5.5 Internal Reset in Watchdog Timer Mode
The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, but TCNT and TSCR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal* is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read RSTCSR after the WDTOVF signal* goes high, then write 0 to the WOVF flag.
Note: * The WDTOVF output function is not available in the F-ZTAT versions.
Rev.7.00 Feb. 14, 2007 page 430 of 1108
REJ09B0089-0700