D12320VF25V Datasheet, PDF (615/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17.5 Register Descriptions
Section 17 ROM
17.5.1 Flash Memory Control Register 1 (FLMCR1)
Bit
:
7
6
5
4
3
2
1
0
FWE SWE ESU PSU
EV
PV
E
P
Initial value : 1/0
0
0
0
0
0
0
0
R/W
:R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the EV or PV bit.
Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally
setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU
bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode
and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and
H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00,
and writes are invalid.
Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV,
and PV only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and
ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1.
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE
0
1
Description
When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and
erasing. This bit should be set when setting FLMCR1 bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits
3 to 0*.
When SWE = 1, the flash memory can only be read in program-verify or erase-verify mode.
Note: * EBR2 bits 5 to 0 should be set in the H8S/2315 F-ZTAT and H8S/2314 F-ZTAT.
Bits 1 and 0 should be set in the H8S/2317 F-ZTAT.
Rev.7.00 Feb. 14, 2007 page 581 of 1108
REJ09B0089-0700