D12320VF25V Datasheet, PDF (475/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Serial Communication Interface (SCI)
12.2.6 Serial Control Register (SCR)
Bit
:
7
6
5
TIE
RIE
TE
Initial value :
0
0
0
R/W
: R/W
R/W
R/W
4
3
2
1
0
RE
MPIE TEIE CKE1 CKE0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode and
module stop mode it retains its previous state.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE
0
Description
Transmit-data-empty interrupt (TXI) requests disabled^*
(Initial value)
1
Transmit-data-empty interrupt (TXI) requests enabled
Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then
clearing it to 0, or by clearing the TIE bit to 0.
Rev.7.00 Feb. 14, 2007 page 441 of 1108
REJ09B0089-0700