D12320VF25V Datasheet, PDF (218/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Data Transfer Controller
7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt controller DTC
Internal address bus
On-chip
RAM
Interrupt
request
CPU interrupt
request
Internal data bus
Legend:
MRA, MRB:
DTC mode registers A and B
CRA, CRB:
DTC transfer count registers A and B
SAR:
DTC source address register
DAR:
DTC destination address register
DTCERA to DTCERE: DTC enable registers A to E
DTVECR:
DTC vector register
Figure 7.1 Block Diagram of DTC
Rev.7.00 Feb. 14, 2007 page 184 of 1108
REJ09B0089-0700