D12320VF25V Datasheet, PDF (11/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Page
12.2.8 Bit Rate
452
Register (BRR)
Table 12.3 BRR
Settings for Various
Bit Rates
(Asynchronous Mode)
14.4.3 Input
545
Sampling and A/D
Conversion Time
Figure 14.5 A/D
Conversion Timing
17.4.1 Features
571
Revision (See Manual for Details)
Table 12.3 amended
Bit Rate
(bits/s)
n
110
3
150
3
300
2
600
2
1200
1
2400
1
4800
0
9600
0
19200
0
31250
0
38400
0
φ = 25 MHz
Error
N
(%)
110 –0.02
80
0.47
162 –0.15
80
0.47
162 –0.15
80
0.47
162 –0.15
80
0.47
40 –0.76
24 0.00
19 1.73
Figure 14.5 amended
(1)
φ
Address bus (2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t _CONV
Description amended
• Reprogramming capability
The flash memory can be reprogrammed a minimum of 100
times.
Rev.7.00 Feb. 14, 2007 page ix of xxxii
REJ09B0089-0700