D12320VF25V Datasheet, PDF (833/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 Clock Pulse Generator
External Clock: The external clock signal should have the same frequency as the system clock
(φ).
Table 18.4 and figure 18.6 show the input conditions for the external clock.
Table 18.4 External Clock Input Conditions
VCC = 2.7 V
to 3.3 V
Item
Symbol Min Max
External clock input
tEXL
low pulse width
20 —
External clock input
tEXH
high pulse width
20 —
External clock rise time tEXr
External clock fall time tEXf
Clock low pulse width tCL
level
—5
—5
0.4 0.6
80 —
Clock high pulse width tCH
level
0.4 0.6
80 —
VCC = 3.0 V
to 3.6 V
Min Max
Unit
Test
Conditions
10 — ns Figure 18.6
10 — ns
— 5 ns
— 5 ns
0.4 0.6 tcyc φ ≥ 5 MHz Figure 20.2
80 — ns φ < 5 MHz
0.4 0.6 tcyc φ ≥ 5 MHz
80 — ns φ < 5 MHz
EXTAL
t_EXH
t_EXL
V_CC × 0.5
t_EXr
t_EXf
Figure 18.6 External Clock Input Timing
Rev.7.00 Feb. 14, 2007 page 799 of 1108
REJ09B0089-0700