D12320VF25V Datasheet, PDF (62/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
• High-speed operation
⎯ All frequently-used instructions execute in one or two states
⎯ Maximum clock rate
: 25 MHz
⎯ 8/16/32-bit register-register add/subtract : 40 ns
⎯ 8 × 8-bit register-register multiply
: 480 ns
⎯ 16 ÷ 8-bit register-register divide
: 480 ns
⎯ 16 × 16-bit register-register multiply : 800 ns
⎯ 32 ÷ 16-bit register-register divide
: 800 ns
• CPU operating mode
⎯ Advanced mode
• Power-down state
⎯ Transition to power-down state by SLEEP instruction
⎯ CPU clock speed selection
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of exection states of the MULXU and MULXS instructions.
Instruction
MULXU
MULXS
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
H8S/2600
3
4
4
5
Internal Operation
H8S/2000
12
20
13
21
There are also differences in the address space, CCR and EXR functions, power-down state, etc.,
depending on the product.
Rev.7.00 Feb. 14, 2007 page 28 of 1108
REJ09B0089-0700