D12320VF25V Datasheet, PDF (1032/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
SCKCR—System Clock Control Register
H'FF3A
Clock Pulse Generator
Bit
:
7
6
5
4
PSTOP ⎯
DIV
⎯
Initial value :
0
0
0
0
Read/Write : R/W
R/W
R/W
⎯
Division
Ratio
Select
Reserved
Only 0 should be
written to this bit
3
2
1
0
⎯
SCK2 SCK1 SCK0
0
0
0
0
⎯
R/W R/W R/W
System Clock Select
DIV = 0
DIV = 1
0 0 0 Bus master is in high-speed mode Bus master is in high-speed mode
1 Medium-speed clock is φ/2
Clock supplied to entire chip is φ/2
1 0 Medium-speed clock is φ/4
Clock supplied to entire chip is φ/4
1 Medium-speed clock is φ/8
Clock supplied to entire chip is φ/8
1 0 0 Medium-speed clock is φ/16
⎯
1 Medium-speed clock is φ/32
⎯
1 ⎯⎯
⎯
φ Clock Output Control
PSTOP Normal Operation
0
φ output
1
Fixed high
Sleep Mode
φ output
Fixed high
Software
Standby Mode
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
Rev.7.00 Feb. 14, 2007 page 998 of 1108
REJ09B0089-0700