D12320VF25V Datasheet, PDF (993/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

MRB—DTC Mode Register B
Appendix B Internal I/O Registers
H'F800—H'FBFF
DTC
Bit
:
Initial value :
Read/Write :
7
6
5
4
3
2
1
0
CHNE DISEL CHNS ⎯
⎯
⎯
⎯
⎯
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Reserved
Only 0 should be written to these bits
DTC Interrupt Select
0 After DTC data transfer ends, the CPU interrupt
is disabled unless the transfer counter is 0
1 After DTC data transfer ends, the CPU interrupt
is enabled
DTC Chain Transfer Enable
DTC Chain Transfer Select
CHNE CHNS
Description
0 ⎯ No chain transfer (At end of DTC data transfer, DTC waits
for activation)
1
0 Chain transfer every time
1
1 Chain transfer only when transfer counter = 0
SAR—DTC Source Address Register
H'F800—H'FBFF
DTC
Bit
: 23 22 21 20 19
---
43210
---
Initial value : Unde- Unde- Unde- Unde- Unde-
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
Read/Write : ⎯ ⎯ ⎯ ⎯ ⎯
---
⎯ ⎯ ⎯⎯ ⎯
Specifies DTC transfer data source address
Rev.7.00 Feb. 14, 2007 page 959 of 1108
REJ09B0089-0700