D12320VF25V Datasheet, PDF (840/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Power-Down Modes
• The division ratio can be changed while the chip is operating. The clock output from the φ pin
will also change when the division ratio is changed. The frequency of the clock output from
the φ pin in this case will be as follows:
φ = EXTAL × n
Where: EXTAL: Crystal resonator or external clock frequency
n:
Division ratio (n = φ/2, φ/4, or φ/8)
• Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits
SCK2 to SCK0.
Bit 5
DIV
0
1
Description
When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed
mode is set
(Initial value)
When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is
supplied to the entire chip
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0,
these bits select the bus master clock; when the DIV bit is set to 1, they select the division ratio of
the clock supplied to the entire chip.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
DIV = 0
DIV = 1
Bus master is in high-speed
Bus master is in high-speed
mode
(Initial value) mode
(Initial value)
Medium-speed clock is φ/2
Clock supplied to entire chip is φ/2
Medium-speed clock is φ/4
Clock supplied to entire chip is φ/4
Medium-speed clock is φ/8
Clock supplied to entire chip is φ/8
Medium-speed clock is φ/16
—
Medium-speed clock is φ/32
—
—
—
Rev.7.00 Feb. 14, 2007 page 806 of 1108
REJ09B0089-0700