D12320VF25V Datasheet, PDF (282/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 I/O Ports
Port 3 Register (PORT3)
Bit
:7
6
5
4
3
2
1
0
—
—
P35
P34
P33
P32
P31
P30
Initial value : Undefined Undefined —^*
—^*
—^*
—^*
—^*
—^*
R/W
:—
—
R
R
R
R
R
R
Note: * Determined by state of pins P35 to P30.
PORT3 is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of
output data for the port 3 pins (P35 to P30) must always be performed on P3DR.
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3
read is performed while P3DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT3 contents are determined by the pin states, as
P3DDR and P3DR are initialized. PORT3 retains its prior state in software standby mode.
Port 3 Open Drain Control Register (P3ODR)
Bit
:7
6
5
4
3
2
1
0
—
— P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value : Undefined Undefined 0
0
0
0
0
0
R/W
:—
—
R/W
R/W
R/W
R/W
R/W
R/W
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3
pin (P35 to P30).
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
Setting P3ODR bits to 1 makes the corresponding port 3 pins NMOS open-drain output pins,
while clearing the bits to 0 makes the pins CMOS output pins.
P3ODR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Rev.7.00 Feb. 14, 2007 page 248 of 1108
REJ09B0089-0700