D12320VF25V Datasheet, PDF (359/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel IOC3 IOC2 IOC1 IOC0 Description
0
0000
TGR0C Output disabled
(Initial value)
1
10
is output _{Initial output is 0 0 output at compare match}
compare
register^*1
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1000
1
1×
1
×
×
TGR0C
is input
capture
register^*
Capture input
source is
TIOCC0 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input Input capture at TCNT1
source is channel count-up/count-down
1/count clock
×: Don’t care
Note: * When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.7.00 Feb. 14, 2007 page 325 of 1108
REJ09B0089-0700