D12320VF25V Datasheet, PDF (694/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
17.16.4 Erase-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for
addresses H'040000 to H'07FFFF)
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared to 0, then
the ESUn bit in FLMCRn is cleared to 0 at least (α) μs later), the watchdog timer is cleared after
the elapse of (β) μs or more, and the operating mode is switched to erase-verify mode by setting
the EVn bit in FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should
be made to the addresses to be read. The dummy write should be executed after the elapse of (γ)
μs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the
data at the latched address is read. Wait at least (ε) μs after the dummy write before performing
this read operation. If the read data has been erased (all 1), a dummy write is performed to the next
address, and erase-verify is performed. If the read data has not been erased, set erase mode again,
and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than (N) times. When verification is completed, exit erase-
verify mode, and wait for at least (η) μs. If erasure has been completed on all the erase blocks,
clear the SWEn bit in FLMCRn to 0 and wait for at least (θ) μs. If there are any unerased blocks,
make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify
sequence in the same way.
Rev.7.00 Feb. 14, 2007 page 660 of 1108
REJ09B0089-0700