D12320VF25V Datasheet, PDF (1069/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCR0—Time Control Register 0
TCR1—Time Control Register 1
Appendix B Internal I/O Registers
H'FFB0
H'FFB1
8-Bit Timer Channel 0
8-Bit Timer Channel 1
Bit
:
Initial value :
Read/Write :
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
3
CCLR1 CCLR0
0
0
R/W R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock Select
0 0 0 Clock input disabled
1 Internal clock: counted at falling edge
of φ/8
1 0 Internal clock: counted at falling edge
of φ/64
1 Internal clock: counted at falling edge
of φ/8192
1 0 0 For channel 0:
Count at TCNT1 overflow signal*
For channel 1:
Count at TCNT0 compare match A*
1 External clock: counted at rising edge
1 0 External clock: counted at falling edge
1 External clock: counted at both rising and
falling edges
Note: * If the count input of channel 0 is the TCNT1 overflow
signal and that of channel 1 is the TCNT0 compare
match signal, no incrementing clock is generated.
Do not use this setting.
Counter Clear
0 0 Clear is disabled
1 Clear by compare match A
1 0 Clear by compare match B
1 Clear by rising edge of external reset input
Timer Overflow Interrupt Enable
0 OVF interrupt requests (OVI) are disabled
1 OVF interrupt requests (OVI) are enabled
Compare Match Interrupt Enable A
0 CMFA interrupt requests (CMIA) are disabled
1 CMFA interrupt requests (CMIA) are enabled
Compare Match Interrupt Enable B
0 CMFB interrupt requests (CMIB) are disabled
1 CMFB interrupt requests (CMIB) are enabled
Rev.7.00 Feb. 14, 2007 page 1035 of 1108
REJ09B0089-0700