D12320VF25V Datasheet, PDF (561/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Smart Card Interface
372 clocks
186 clocks
0
185
371 0
Internal
base
clock
Receive
data (RxD)
Start bit
D0
185
371 0
D1
Synchro-
nization
sampling
timing
Data
sampling
timing
Figure 13.10 Receive Data Sampling Timing in Smart Card Mode
(When Using 372-Times Clock)
Thus the receive margin in asynchronous mode is given by the following formula.
1
⎥ D – 0.5⎥
M =⎥ (0.5 –
) – (L – 0.5) F –
(1 + F)⎥ × 100%
2N
N
Where M: Receive margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N=372 in the above formula, the receive margin formula
is as follows.
When D = 0.5 and F = 0,
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Rev.7.00 Feb. 14, 2007 page 527 of 1108
REJ09B0089-0700