D12320VF25V Datasheet, PDF (219/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Data Transfer Controller
7.1.3 Register Configuration
Table 7.1 summarizes the DTC registers.
Table 7.1 DTC Registers
Name
DTC mode register A
DTC mode register B
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
Abbreviation
MRA
MRB
SAR
DAR
CRA
CRB
R/W
—^*2
—^*2
—^*2
—^*2
—^*2
—^*2
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Address^*1
—^*3
—^*3
—^*3
—^*3
—^*3
—^*3
DTC enable registers
DTCER
R/W H'00
H'FF30 to H'FF34
DTC vector register
DTVECR
R/W H'00
H'FF37
Module stop control register
MSTPCR
R/W H'3FFF
H'FF3C
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot
be located in external space. When the DTC is used, do not clear the RAME bit in
SYSCR to 0.
Rev.7.00 Feb. 14, 2007 page 185 of 1108
REJ09B0089-0700