D12320VF25V Datasheet, PDF (184/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
0
1
Description
Max. 4 words in burst access
Max. 8 words in burst access
(Initial value)
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
6.2.5 Bus Control Register L (BCRL)
Bit
:
7
6
5
4
3
2
1
0
BRLE BREQOE EAE
—
—
—
— WAITE
Initial value :
0
0
1
1
1
1
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area division unit, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Description
External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
(Initial value)
External bus release is enabled
Rev.7.00 Feb. 14, 2007 page 150 of 1108
REJ09B0089-0700