D12320VF25V Datasheet, PDF (196/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D₁₅ to D₈) of the data bus is used
for the even address, and the lower half (D₇ to D₀) for the odd address.
Wait states cannot be inserted.
Bus cycle
T₁
T₂
φ
Address bus
CSn
AS
RD
Read
D₁₅ to D₈
Valid
D₇ to D₀
Invalid
HWR
Write
LWR
D₁₅ to D₈
High
Valid
D₇ to D₀
High impedance
Note: n = 0 to 7
Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
Rev.7.00 Feb. 14, 2007 page 162 of 1108
REJ09B0089-0700