D12320VF25V Datasheet, PDF (389/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.5 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 9.6 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
Table 9.6 Cascaded Combinations
Combination
Channels 1 and 2
Channels 4 and 5
Upper 16 Bits
TCNT1
TCNT4
Lower 16 Bits
TCNT2
TCNT5
Example of Cascaded Operation Setting Procedure: Figure 9.21 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
Start count
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'111 to select TCNT2
(TCNT5) overflow/underflow counting.
[1] _{[2] Set the CST bit in TSTR for the upper and lower}
channel to 1 to start the count operation.
[2]
<Cascaded operation>
Figure 9.21 Cascaded Operation Setting Procedure
Rev.7.00 Feb. 14, 2007 page 355 of 1108
REJ09B0089-0700