D12320VF25V Datasheet, PDF (320/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 I/O Ports
Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For
details, see section 8.12, Port G.
Bit 6—CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For
details, see section 8.12, Port G.
Bit 5—Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output.
This bit is valid in modes 4 to 6.
Bit 5
PF1CS5S
0
1
Description
PF1 is the PF1/BACK/IRQ1 pin
(Initial value)
PF1 is the PF1/BACK/IRQ1/CS5 pin. CS5 output is enabled when BRLE = 0,
CS25E = 1, and PF1DDR = 1
Bit 4—Port F0 Chip Select 4 Select (PF0CS4S): Selects enabling or disabling of CS4 output.
This bit is valid in modes 4 to 6.
Bit 4
PF0CS4S
0
1
Description
PF0 is the PF0/BREQ/IRQ0 pin
(Initial value)
PF0 is the PF0/BREQ/IRQ0/CS4 pin. CS4 output is enabled when BRLE = 0,
CS25E = 1, and PF0DDR = 1
Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23). For details, see
section 8.2, Port 1.
Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A22). For details, see
section 8.2, Port 1.
Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). For details, see
section 8.2, Port 1.
Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). For details, see
section 8.2, Port 1.
Rev.7.00 Feb. 14, 2007 page 286 of 1108
REJ09B0089-0700