D12320VF25V Datasheet, PDF (213/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.7.4 Transition Timing
Figure 6.19 shows the timing for transition to the bus released state.
Section 6 Bus Controller
φ
Address bus
Data bus
AS
RD
HWR, LWR
CPU cycle
T₀
T₁
T₂
Address
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
CPU
cycle
BREQ
BACK
BREQO^*
Minimum
1 state
[1]
[2]
[3]
[4]
[5]
[6]
[1] Low level of BREQ pin is sampled at rise of T₂ state.
[2] BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
[3] BREQ pin state is still sampled in external bus released state.
[4] High level of BREQ pin is sampled.
[5] BACK pin is driven high, ending bus release cycle.
[6] BREQO signal goes high 1.5 clocks after BACK signal goes high.
Note: * Output only when BREQOE is set to 1.
Figure 6.19 Bus Released State Transition Timing
Rev.7.00 Feb. 14, 2007 page 179 of 1108
REJ09B0089-0700