D12320VF25V Datasheet, PDF (388/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
• When TGR is an input capture register
Figure 9.20 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
TGRC
H'0532
H'0F07
H'0532
Figure 9.20 Example of Buffer Operation (2)
H'09FB
H'0F07
Rev.7.00 Feb. 14, 2007 page 354 of 1108
REJ09B0089-0700