D12320VF25V Datasheet, PDF (246/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Data Transfer Controller
Chain Transfer when Counter = 0: By executing a second data transfer, and performing re-
setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or
more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 7.13 shows the memory map.
[1] For the first transfer, set the normal mode for input data. Set fixed transfer source address
(G/A, etc.), CRA = H'0000 (64k times), and CHNE = 1, CHNS = 1, and DISEL = 0.
[2] Prepare the upper 8-bit addresses of the start addresses for each of the 64k transfer start
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
[3] For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
[4] Execute the first data transfer 64k times by means of interrupts. When the transfer counter for
the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the
transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
[5] Next, execute the first data transfer the 64k times specified for the first data transfer by means
of interrupts. When the transfer counter for the first data transfer reaches 0, the second data
transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to
H'20. The lower 16 bits of the transfer destination address of the first data transfer and the
transfer counter are H'0000.
[6] Steps [4] and [5] are repeated endlessly. As repeat mode is specified for the second data
transfer, an interrupt request is not sent to the CPU.
Rev.7.00 Feb. 14, 2007 page 212 of 1108
REJ09B0089-0700