D12320VF25V Datasheet, PDF (1052/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
SSR0—Serial Status Register 0
H'FF7C
SCI0
Bit
:
Initial value :
Read/Write :
7
TDRE
1
R/(W)^*
6
RDRF
0
R/(W)^*
5
ORER
0
R/(W)^*
4
FER
0
R/(W)^*
3
PER
0
R/(W)^*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
When data with a 0 multiprocessor bit is received^*
1 [Setting condition]
When data with a 1 multiprocessor bit is received
Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with a
multiprocessor format.
Transmit End
0 [Clearing conditions]
· When 0 is written to TDRE after reading TDRE = 1
· When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions]
· When the TE bit in SCR is 0
· When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
Parity Error
0 [Clearing condition]
When 0 is written to PER after reading PER = 1^*1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR^*2
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in
SCR is cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag
is not set. Serial reception cannot be continued while the PER flag is set to 1.
In synchronous mode, serial transmission is also disabled.
Framing Error
0 [Clearing condition]
When 0 is written to FER after reading FER = 1^*1
1 [Setting condition]
When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0^*2
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial
reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission
is also disabled.
Overrun Error
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1^*1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1^*2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and data received subsequently is lost.
Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission
is also disabled.
Receive Data Register Full^*
0 [Clearing conditions]
· When 0 is written to RDRF after reading RDRF = 1
· When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: * RDR and the RDRF flag are not affected and retain their previous values when an
error is detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an
overrun error will occur and the receive data will be lost.
Transmit Data Register Empty
0 [Clearing conditions]
· When 0 is written to TDRE after reading TDRE = 1
· When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions]
· When the TE bit in SCR is 0
· When data is transferred from TDR to TSR and data can be written to TDR
Note: * Can only be written with 0 for flag clearing.
Rev.7.00 Feb. 14, 2007 page 1018 of 1108
REJ09B0089-0700