D12320VF25V Datasheet, PDF (1073/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCNT—Timer Counter
Bit
:7
6
Appendix B Internal I/O Registers
H'FFBC (W), H'FFBD (R)
WDT
5
4
3
2
1
0
Initial value : 0
0
0
0
0
0
0
0
Read/Write : R/W
R/W R/W
R/W R/W
R/W
R/W R/W
Note: The method for writing to TCNT different from that for general registers to prevent
accidental overwritting. For details, see section 11.2.4, Notes on Register Access.
RSTCSR—Reset Control/Status Register H'FFBE (W), H'FFBF (R)
Bit
:
7
6
5
4
3
2
1
WOVF RSTE ⎯
⎯
⎯
⎯
⎯
Initial value :
0
0
0
1
1
1
1
Read/Write : _{R/(W)* R/W R/W}
⎯
⎯
⎯
⎯
WDT
0
⎯
1
⎯
Reserved
This bit should be written with 0.
Reset Enable
0 Reset signal is not generated if TCNT overflows*
1 Reset signal is generated if TCNT overflows
Note: * The modules in the chip are not reset,
but TCNT and TCSR in WDT are reset.
Watchdog Timer Overflow Flag
0 [Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF.
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00) during
watchdog timer operation
Notes: The method for writing to RSTCSR is different from that for general registers to prevent
accidental overwriting. For details, see section 11.2.4, Notes on Register Access.
* Can only be written with 0 for flag clearing.
Rev.7.00 Feb. 14, 2007 page 1039 of 1108
REJ09B0089-0700