D12320VF25V Datasheet, PDF (539/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Smart Card Interface
Bit 4
ERS
Description
0
Indicates data received normally with no error signal
[Clearing conditions]
(Initial value)
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
1
Indicates an error signal was sent showing detection of a parity error at the receiving
side
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
state.
Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial
Status Register (SSR).
However, the setting conditions for the TEND bit, are as shown below.
Bit 2
TEND
Description
0
Indicates transfer in progress
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1
Indicates transfer complete
[Setting conditions]
(Initial value)
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a
1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a
1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1 and BLK = 1
Note: etu: Elementary time unit (time for transfer of 1 bit)
Rev.7.00 Feb. 14, 2007 page 505 of 1108
REJ09B0089-0700