D12320VF25V Datasheet, PDF (443/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 8-Bit Timers
10.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 10.11 shows this operation.
TCNT write cycle by CPU
T₁
T₂
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 10.11 Contention between TCNT Write and Increment
Rev.7.00 Feb. 14, 2007 page 409 of 1108
REJ09B0089-0700