D12320VF25V Datasheet, PDF (145/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.1.3 Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Interrupt Controller Pins
Name
Symbol
Nonmaskable interrupt NMI
I/O
Input
External interrupt
requests 7 to 0
IRQ7 to IRQ0 Input
Function
Nonmaskable external interrupt; rising or
falling edge can be selected
Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected
5.1.4 Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2 Interrupt Controller Registers
Name
Abbreviation R/W
System control register
SYSCR
R/W
IRQ sense control register H ISCRH
R/W
IRQ sense control register L ISCRL
R/W
IRQ enable register
IER
IRQ status register
ISR
R/W
R/(W)^*2
Interrupt priority register A
IPRA
R/W
Interrupt priority register B
IPRB
R/W
Interrupt priority register C
IPRC
R/W
Interrupt priority register D
IPRD
R/W
Interrupt priority register E
IPRE
R/W
Interrupt priority register F
IPRF
R/W
Interrupt priority register G
IPRG
R/W
Interrupt priority register H
IPRH
R/W
Interrupt priority register I
IPRI
R/W
Interrupt priority register J
IPRJ
R/W
Interrupt priority register K
IPRK
R/W
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clearing.
Initial Value
H'01
H'00
H'00
H'00
H'00
H'77
H'77
H'77
H'77
H'77
H'77
H'77
H'77
H'77
H'77
H'77
Address^*1
H'FF39
H'FF2C
H'FF2D
H'FF2E
H'FF2F
H'FEC4
H'FEC5
H'FEC6
H'FEC7
H'FEC8
H'FEC9
H'FECA
H'FECB
H'FECC
H'FECD
H'FECE
Rev.7.00 Feb. 14, 2007 page 111 of 1108
REJ09B0089-0700