D12320VF25V Datasheet, PDF (681/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17.14.5 System Control Register 2 (SYSCR2)
Bit
:
7
6
5
4
3
2
—
—
—
— FLSHE —
Initial value :
0
0
0
0
0
0
R/W
:—
—
—
—
R/W
—
Section 17 ROM
1
0
—
—
0
0
—
R/W
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 can only be used in the F-ZTAT version. In the mask ROM version this register will
return an undefined value if read, and cannot be modified.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit
enables the flash memory control registers to be read and written to. Clearing FLSHE to 0
designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE
0
1
Description
Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
(Initial value)
Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Reserved: Only 0 should be written.
17.14.6 RAM Emulation Register (RAMER)
Bit
:
7
6
5
4
—
—
—
—
Initial value :
0
0
0
0
R/W
:—
—
—
—
3
RAMS
0
R/W
2
RAM2
0
R/W
1
RAM1
0
R/W
0
RAM0
0
R/W
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
Rev.7.00 Feb. 14, 2007 page 647 of 1108
REJ09B0089-0700