D12320VF25V Datasheet, PDF (690/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
17.16 Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for
addresses H'000000 to H'03FFFF by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in
FLMCR1, and for addresses H'040000 to H'07FFFF by setting the PSU2, ESU2, P2, E2, PV2, and
EV2 bits in FLMCR2.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM, external memory, or flash memory except for the above
address areas. When the program is located in external memory, an instruction for programming
the flash memory and the following instruction should be located in on-chip RAM. The DTC
should not be activated before or after the instruction for programming the flash memory is
executed.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1,
E1, and P1 bits in FLMCR1 or setting/resetting of the SWE2, ESU2, PSU2, EV2, PV2,
E2, and P2 bits in FLMCR2 is executed by a program in flash memory.
2. Perform programming in the erased state. Do not perform additional programming on
previously programmed addresses.
3. Do not program addresses H'000000 to H'03FFFF and H'040000 to H'07FFFF
simultaneously. Operation is not guaranteed when programming is performed
simultaneously.
17.16.1 Program Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for
addresses H'040000 to H'07FFFF)
Follow the procedure shown in the program/program-verify flowchart in figure 17.45 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
For the wait times (x, y, z1, z2, z3 α, ß, γ, ε, η, and θ) after bits are set or cleared in flash memory
control register n (FLMCRn) and the maximum number of programming operations (N), see
section 20.3.6, Flash Memory Characteristics.
Following the elapse of (x) μs or more after the SWEn bit is set to 1 in flash memory control
register n (FLMCRn), 128-byte program data is stored in the program data area and reprogram
Rev.7.00 Feb. 14, 2007 page 656 of 1108
REJ09B0089-0700