D12320VF25V Datasheet, PDF (892/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Electrical Characteristics
(4) Timing of On-Chip Supporting Modules
Table 20.26 Timing of On-Chip Supporting Modules
Condition B: V_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS =
0 V, φ = 2 MHz to 25 MHz, T_a = –20°C to 75°C (regular specifications),
T_a = –40°C to 85°C (wide-range specifications)
Item
Symbol Min
I/O ports Output data delay time
tPWD
—
Input data setup time
tPRS
25
Input data hold time
tPRH
25
TPU
Timer output delay time
tTOCD
—
Timer input setup time
tTICS
25
Timer clock input setup time
tTCKS
25
Timer clock Single-edge
tTCKWH
1.5
pulse width specification
Both-edge
tTCKWL
2.5
specification
8-bit timer Timer output delay time
tTMOD
—
Timer reset input setup time
tTMRS
25
Timer clock input setup time
tTMCS
25
Timer clock Single-edge
tTMCWH
1.5
pulse width specification
Both-edge
tTMCWL
2.5
specification
SCI
Input clock Asynchronous tScyc
4
cycle
Synchronous
6
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
tSCKW
0.4
tSCKr
—
tSCKf
—
tTXD
—
tRXS
40
Receive data hold time
(synchronous)
tRXH
40
A/D
converter
Trigger input setup time
tTRGS
30
Max
40
—
—
40
—
—
—
—
40
—
—
—
—
—
—
0.6
1.5
1.5
40
—
—
—
Unit Test Conditions
ns
Figure 20.13
ns
ns
ns
Figure 20.14
ns
ns
Figure 20.15
tcyc
tcyc
ns
Figure 20.16
ns
Figure 20.18
ns
Figure 20.17
tcyc
tcyc
tcyc
Figure 20.20
tcyc
tScyc
tcyc
tcyc
ns
Figure 20.21
ns
ns
ns
Figure 20.22
Rev.7.00 Feb. 14, 2007 page 858 of 1108
REJ09B0089-0700