D12320VF25V Datasheet, PDF (990/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
Module Register
Abbreviation R/W Initial Value Address^*1
Port E
Port E data direction register
PEDDR
W
H'00
H'FEBD
Port E data register
PEDR
R/W H'00
H'FF6D
Port E register
PORTE
R
Undefined H'FF5D
Port F
Port E MOS pull-up control register PEPCR
Port F data direction register
PFDDR
R/W H'00
H'FF74
W
H'80/H'00^*17 H'FEBE
Port F data register
PFDR
R/W H'00
H'FF6E
Port F register
PORTF
R
Undefined H'FF5E
Port function control register 1
PFCR1
R/W H'0F
H'FF45
Port function control register 2
PFCR2
R/W H'30
H'FFAC
System control register
SYSCR
R/W H'01
H'FF39
Port G
Port G data direction register
PGDDR
W
H'10/H'00 H'FEBF
*¹⁷ *¹⁸
Port G data register
Port G register
PGDR
PORTG
R/W
R
H'00^*18
H'FF6F
Undefined^*18 H'FF5F
Port function control register 1
PFCR1
R/W H'0F
H'FF45
Port function control register 2
PFCR2
R/W H'30
H'FFAC
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written for flag clearing.
3. Registers in the DTC cannot be read or written to directly.
4. Located as register information in on-chip RAM addresses H'EBC0 to H'EFBF. Cannot
be located in external memory space. Do not clear the RAME bit in SYSCR to 0 when
using the DTC.
5. Determined by the MCU operating mode.
6. Bits used for pulse output cannot be written to.
7. Only 0 can be written to bits 7 to 5, to clear the flags.
8. For information on writing, see section 11.2.4, Notes on Register Access.
9. Only 0 can be written to bit 7, to clear the flag.
10. Flash memory registers selection is performed by means of the FLSHE bit in system
control register 2 (SYSCR2).
11. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit in FLMCR1 is cleared to
0 (except for the H8S/2319 F-ZTAT).
12. In the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-
ZTAT when a high level is input to the FWE pin, the initial value is H'80. In the
H8S/2319 F-ZTAT, the initial value is H'80.
13. In the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-
ZTAT when a low level is input to the FWE pin, or if a high level is input but the SWE
bit in FLMCR1 is not set, these registers are initialized to H'00.
Rev.7.00 Feb. 14, 2007 page 956 of 1108
REJ09B0089-0700