D12320VF25V Datasheet, PDF (697/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
17.17.2 Software Protection
Software protection can be implemented by setting the SWE1 bit in flash memory control register
1 (FLMCR1), SWE2 bit in FLMCR2 erase block registers 1 and 2 (EBR1, EBR2), and the RAMS
bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1
or E1 bit in FLMCR1, or the P2 or E2 bit in FLMCR2 does not cause a transition to program
mode or erase mode (see table 17.33).
Table 17.33 Software Protection
Functions
Item
Description
Program Erase
SWE bit protection • Clearing the SWE1 bit to 0 in FLMCR1 sets Yes
Yes
the program/erase-protected state for area
H'000000 to H'03FFFF (Execute in on-chip
RAM, external memory, or addresses
H'040000 to H'07FFFF)
• Clearing the SWE2 bit to 0 in FLMCR2 sets
the program/erase-protected state for area
H'040000 to H'07FFFF (Execute in on-chip
RAM, external memory, or addresses
H'000000 to H'03FFFF)
Block specification • Erase protection can be set for individual —
Yes
protection
blocks by settings in erase block registers 1
and 2 (EBR1, EBR2).
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Emulation protection • Setting the RAMS bit to 1 in the RAM
Yes
Yes
emulation register (RAMER) places all blocks
in the program/erase-protected state.
Rev.7.00 Feb. 14, 2007 page 663 of 1108
REJ09B0089-0700