D12320VF25V Datasheet, PDF (547/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Smart Card Interface
13.3.4 Register Settings
Table 13.3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 13.3 Smart Card Interface Register Settings
Bit
Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SMR
GM
BLK
1
O/E
BCP1 BCP0 CKS1
BRR
SCR
BRR7
TIE
BRR6
RIE
BRR5
TE
BRR4
RE
BRR3
0
BRR2
0
BRR1
CKE1^*
TDR
TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1
SSR
TDRE RDRF ORER ERS
PER
TEND 0
RDR
RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1
SCMR
—
—
—
—
SDIR SINV —
Notes: — : Unused bit.
* The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
SMR Settings: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in
GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1
if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator, and bits BCP1
and BCP0 select the number of base clock cycles during transfer of one bit. For details, see section
13.3.5, Clock.
The BLK bit is cleared to 0 when using the normal smart card interface mode, and set to 1 when
using block transfer mode.
BRR Setting: BRR is used to set the bit rate. See section 13.3.5, Clock, for the method of
calculating the value to be set.
SCR Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 12, Serial Communication Interface (SCI).
Rev.7.00 Feb. 14, 2007 page 513 of 1108
REJ09B0089-0700