D12320VF25V Datasheet, PDF (867/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Electrical Characteristics
(4) Timing of On-Chip Supporting Modules
Table 20.7 Timing of On-Chip Supporting Modules
Condition A: V_CC = 2.7 V to 3.6 V, AV_CC = 2.7 V to 3.6 V, V_ref = 2.7 V to AV_CC, V_SS = AV_SS =
0 V, φ = 2 MHz to 20 MHz, T_a = –20°C to 75°C (regular specifications),
T_a = –40°C to 85°C (wide-range specifications)
Condition B: V_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS =
0 V, φ = 2 MHz to 25 MHz, T_a = –20°C to 75°C (regular specifications),
T_a = –40°C to 85°C (wide-range specifications)
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
TPU
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock Single-edge
pulse width specification
Both-edge
specification
8-bit timer Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock Single-edge
pulse width specification
Both-edge
specification
WDT
Overflow output delay time
Condition A
Symbol Min Max
tPWD
—
50
tPRS
30
—
tPRH
30
—
tTOCD
—
50
tTICS
30
—
tTCKS
30
—
tTCKWH
1.5
—
tTCKWL
2.5
—
tTMOD
—
50
tTMRS
30
—
tTMCS
30
—
tTMCWH
1.5
—
tTMCWL
2.5
—
tWOVD
—
50
Condition B
Test
Min Max Unit Conditions
—
40
ns Figure 20.13
25
—
ns
25
—
ns
—
40
ns Figure 20.14
25
—
ns
25
—
ns Figure 20.15
1.5 —
tcyc
2.5 —
tcyc
—
40
25
—
25
—
1.5 —
ns Figure 20.16
ns Figure 20.18
ns Figure 20.17
tcyc
2.5 —
tcyc
—
40
ns Figure 20.19
Rev.7.00 Feb. 14, 2007 page 833 of 1108
REJ09B0089-0700