D12320VF25V Datasheet, PDF (438/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 8-Bit Timers
10.3.3 Timing of TCNT External Reset
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10.7
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N−1
N
H'00
Figure 10.7 Timing of Clearance by External Reset
10.3.4 Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 10.8
shows the timing of this operation.
φ
TCNT
Overflow signal
H'FF
H'00
OVF
Figure 10.8 Timing of OVF Setting
Rev.7.00 Feb. 14, 2007 page 404 of 1108
REJ09B0089-0700