D12320VF25V Datasheet, PDF (456/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Watchdog Timer
Bit 5—Reserved: This bit should be written with 0.
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
11.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.
They cannot be written to with byte instructions.
Figure 11.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
TCNT write
15
Address: H'FFBC
H'5A
87
0
Write data
TCSR write
15
Address: H'FFBC
H'A5
87
0
Write data
Figure 11.2 Writing to TCNT and TCSR
Writing to RSTCSR: RSTCSR must be written to by a word transfer instruction to address
H'FFBE. It cannot be written to with byte instructions.
Figure 11.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF
bit differs from that for writing to the RSTE bit.
To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the
lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the
RSTE bit, the upper byte must contain H'5A and the lower byte must contain the write data. This
writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit.
Rev.7.00 Feb. 14, 2007 page 422 of 1108
REJ09B0089-0700