D12320VF25V Datasheet, PDF (97/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
End of bus request
Bus request
End of bus
request
Bus-released state
Program execution
state
Bus
request
SLEEP
instruction
with
SLEEP _{SSBY = 0}
instruction
with
SSBY = 1
End of
exception
handling
Request for
exception
handling
Sleep mode
Exception-handling state
Interrupt
request
External interrupt
Software standby mode
RES = high
Reset state^*1
STBY = high, RES = low
Hardware standby mode^*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.12 State Transitions
2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11,
Watchdog Timer.
Rev.7.00 Feb. 14, 2007 page 63 of 1108
REJ09B0089-0700