D12320VF25V Datasheet, PDF (483/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.2.8 Bit Rate Register (BRR)
Bit
:
7
6
5
Section 12 Serial Communication Interface (SCI)
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in hardware standby mode. In software standby mode
and module stop mode it retains its previous state.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 12.3 shows sample BRR settings in asynchronous mode, and table 12.4 shows sample BRR
settings in synchronous mode.
Rev.7.00 Feb. 14, 2007 page 449 of 1108
REJ09B0089-0700