D12320VF25V Datasheet, PDF (346/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
CKEG1
Bit 3
CKEG0
Description
0
0
Count at rising edge
(Initial value)
1
Count at falling edge
1
—
Count at both edges
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 9.4 shows the clock
sources that can be set for each channel.
Table 9.4 TPU Clock Sources
Internal Clock
External Clock
Overflow/
Underflow
Channel φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA TCLKB TCLKC TCLKD ^{on Another}
Channel
0
1
2
3
4
5
Legend:
: Setting
Blank: No setting
Rev.7.00 Feb. 14, 2007 page 312 of 1108
REJ09B0089-0700